`include "PRV564Config.v"
`include "PRV564Define.v"
module InformCSR
#(
    parameter HARTID = 64'h0
)
(
    input wire              CLKi, ARSTi,        //clock and global reset
    output wire [`XLEN-1:0] mhartid, mvendorid, marchid, 
    output reg  [`XLEN-1:0] mimpid,
    output reg              CSR_InhibitIcache,  //Inhibit I Cache
    output reg              CSR_InhibitDcache,  //Inhibit D Cache
    output reg              CSR_DCacheWT,       //D Cache force Write Through mode
    //----------write back---------------
    input wire [11:0]       csr_index,
    input wire [`XLEN-1:0]  csr_data,
    input wire              csr_wren
);

    reg [7:0] eva;
always@(posedge CLKi or posedge ARSTi)begin
    if(ARSTi)begin
        eva <= 8'hff;
    end
    else if(csr_wren)begin
        if(csr_index == `mrw_evangelion_index)begin
            eva <= csr_data[7:0];
        end
    end
end

always@(*)begin
    case(eva)
        8'd0 : mimpid = 64'h004179616e616d69;
        8'd1 : mimpid = 64'h00005368696e6a69;
        8'd2 : mimpid = 64'h0000004173756b61;
    default  : mimpid = 64'h0000000000000000;
    endcase
end

always@(posedge CLKi or posedge ARSTi)begin
    if(ARSTi)begin
        CSR_InhibitIcache   <= `ICacheForceInhibit;
        CSR_InhibitDcache   <= `DCacheForceInhibit;
        CSR_DCacheWT        <= `CacheWTDefaultSwitch;
    end
    else if(csr_wren)begin
        if(csr_index == `mrw_kernelcfg_index)begin
            CSR_InhibitIcache   <= csr_data[0];
            CSR_InhibitDcache   <= csr_data[2];
            CSR_DCacheWT        <= csr_data[4];
        end
    end
end

assign mhartid      = HARTID;
assign mvendorid    = 64'h004b6f726f6c6576;     //VID : Korolev
assign marchid      = 64'h0000566f73746f6b;     //arch: Vostok

endmodule
